Verigy 93k Tester Manual [exclusive] Jun 2026

Which you are using ( SmarTest 7 or SmarTest 8 )?

Allows different pin groups to run at completely independent frequencies, facilitating multi-port testing. Key Instrumentation Classes

[Define Pin Map] ➔ [Configure Levels & Timing] ➔ [Load Digital Vectors] ➔ [Develop Test Methods] ➔ [Construct Test Flow]

Chain your functional and parametric tests together. For custom evaluations, use C++ or Java-based API. Test methods read physical characteristics (like continuity or leakage) and return structural pass/fail or logging data to the main thread. 4. Fundamental Test Methodologies verigy 93k tester manual

The manual is a vital tool for diagnosing issues and keeping the tester in optimal condition:

Cyclical digital patterns (commonly derived from WGL or STIL files via EDA tools) are compiled into the binary formats required by the tester memory.

Dedicated channels optimized to provide clean, programmable power to the Device Under Test (DUT) with precise current monitoring. 2. Navigating the Verigy 93k Documentation Tree Which you are using ( SmarTest 7 or SmarTest 8 )

93k Tester 02 Hardware Overview Rev.7.2.2.A.00 | PDF - Scribd

Allows engineers to manually force states on a pin or step through digital vector files cycle-by-cycle to ensure the hardware is performing as intended. Best Practices for Optimization

: Engineers use SmarTest to define "test flows" and "test suites." These organize how the hardware interacts with the Device Under Test (DUT). For custom evaluations, use C++ or Java-based API

If you need help optimizing specific sections of your test program, please let me know:

Maps the logical names of the DUT pins to the physical channels on the tester cards.

: If you have the SmarTest software installed, go to Help > Help Contents to open the integrated documentation.