Eyeq4 | Datasheet

6 cores dedicated to VLIW and SIMD operations, ideal for short integral types in vision algorithms. Multi-threaded Processor Cluster

+-----------------------------------------------------------------------+ | MOBILEYE EYEQ4 ARCHITECTURE | +-----------------------------------------------------------------------+ | [ General-Purpose Control ] | | - MIPS interAptiv 64-bit RISC CPU (Multi-threaded cores) | +-----------------------------------------------------------------------+ | [ Heterogeneous Vision Accelerator Pipeline ] | | - Vector Microcode Processors (VMP): VLIW/SIMD pixel manipulation | | - Multithreaded Processing Clusters (MPC): Task-specific execution | | - Programmable Macro Arrays (PMA): High-density dataflow engine | | - XNN Deep Learning Accelerator: Convolutional Neural Network (CNN) | +-----------------------------------------------------------------------+ | [ Memory & Interface I/O ] | | - Dual LPDDR4 Interfaces - 4x MIPI CSI-2 Rx - Tri-CAN / Gigabit Enet | +-----------------------------------------------------------------------+

Last updated: October 2024. Specifications subject to change by manufacturer.

The EyeQ4 is manufactured using (Fully Depleted Silicon On Insulator) process, which is critical for achieving high performance at low power. Specification Performance 2.5 TOPS (Tera Operations Per Second) Power Consumption ~3 Watts (nominal) Process Node 28nm FD-SOI Camera Support Up to 8 cameras simultaneously Frame Rate 36 fps (at max camera load) Package 784-pin Flip-Chip FBGA (22.5 x 22.5 mm) Safety Grade ASIL-B & AEC-Q100 Grade 2 架构组成 (Processor Architecture) eyeq4 datasheet

: Features four multi-threaded MIPS I6500 CPU cores (interlinked in a coherent cluster). These cores handle high-level application code, operating system tasks, and sensor fusion algorithms.

The chip incorporates . The PMA provides compute density similar to fixed-function hardware but retains software programmability. It acts as an accelerator for deep learning layers, particularly pooling, convolutions, and fully connected layers found in modern Deep Neural Networks (DNNs). Multi-Threaded Processing Cores (MPC)

Unlike general-purpose CPUs or graphics-heavy GPUs, the EyeQ4 utilizes a highly specialized, heterogeneous architecture. It balances programmable compute cores with dedicated hardware accelerators to maximize efficiency. Heterogeneous Compute Blocks 6 cores dedicated to VLIW and SIMD operations,

Produced by STMicroelectronics using a proprietary 28nm process.

: Powers technologies like Autonomous Emergency Braking (AEB), next-generation lane detection, and vehicle detection from any angle.

This technical guide unpacks the architectural blocks, peripheral interfaces, pin layouts, and application standards defined across the EyeQ4 processor family variants. Hardware Architecture and Compute Subsystem The EyeQ4 is manufactured using (Fully Depleted Silicon

Two PMA cores acting as a Coarse-Grained Reconfigurable Array (CGRA) dataflow machine, accelerating dense computer vision and deep learning data pipelines.

: Used in configurations ranging from a single "Mono" camera for collision avoidance to "Tricam" setups for semi-autonomous driving.

Next-generation lane and road boundary detection for centering and departure warnings.

The datasheet details the Mobileye EyeQ4’s Image Signal Processor (ISP). It supports up to 8x MIPI CSI-2 lanes. Critical specs include: